This invention relates to a radio receiving apparatus and, more particularly, to a radio receiving apparatus having a clock regenerating circuit for regenerating a clock, which is synchronized to a symbol clock on the transmitting side, and identifying a demodulated signal by the timing of the regenerated clock.
A clock regenerating circuit used in the receiver section of a multiplexed radio apparatus is referred to also as a BTR (Bit Timing Recovery) circuit and is used to regenerate a clock component from a signal obtained by demodulating a multilevel quadrature modulated signal such as a signal modulated by PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). The clock regenerated by the clock regenerating circuit is used as the operation timing signal of a device such as an AD converter for identifying a demodulated signal. To this end, it is required that the phase of the regenerated clock be made to coincide with the timing at which the level of the demodulated signal is identified (which timing is the moment at which the so-called eye pattern is open to the maximum extent). However, owing to changes in line conditions such as caused by a change in temperature, there are instances where the clock develops a phase shift. Accordingly, there is demand for a clock regenerating circuit that is capable of regenerating a highly precise signal discriminating clock by detecting such a phase shift in highly accurate fashion and compensating for the clock phase shift in an accurate matter.
FIG. 19 is a diagram showing the construction of the receiver section of a multiplexed radio apparatus according to the prior art. The receiver section has a clock regenerating circuit for identifying a demodulated signal in highly precise fashion.
(a) Overall Configuration
An intermediate-frequency signal IF-IN is obtained by applying frequency modulation to a received signal. The received signal has been subjected to multilevel quadrature modulation such as PSK or QAM (e.g., 16 QAM).
A quadrature detector 22 orthogonally detects the intermediate-frequency signal IF-IN and outputs two types of baseband signals (an I-channel signal Ich and a Q-channel signal Qch), which are 90.degree. out of phase (i.e., in quadrature). AD converters 23, 24 respectively convert the I- and Q-channel signals Ich, Qch, which are output by the quadrature detector 22, to digital data. A transversal equalizer 25 applies equalization processing to the digital data output by the AD converters 23, 24. A clock phase signal generator 26 detects the phase components of a regenerated clock and outputs a clock phase signal. A clock regenerating circuit 27 regenerates a clock signal CLK synchronized to symbol clock that is included in the demodulated signal.
(b) Quadrature Detector
The quadrature detector 22 includes an intermediate-frequency amplifier 22a, a hybrid circuit (H) 22b for branching the intermediate-frequency signal, a local oscillator 22c, which oscillates at a carrier frequency fc, a hybrid circuit 22d for separating the output signal of the local oscillator 22c into two signals that are 90.degree. out of phase, mixer circuits 22e, 22f for orthogonally detecting the intermediate-frequency signal by mixing it with two orthogonal signals and outputting baseband in-phase and quadrature signals Ich, Qch, respectively, and roll-off filters 22g, 22h for imparting a roll-off characteristic to the baseband in-phase and quadrature signals Ich, Qch.
(c) Transversal Equalizer
The transversal equalizer 25 has the construction of a well-known two-dimensional transversal equalizer of the kind shown in FIG. 20. The transversal equalizer includes transversal filters 25a-1, 25a-2 for eliminating transmission path distortion of the I-channel signal, transversal filters 25b-1, 25ba-2 for eliminating transmission path distortion of the Q-channel signal, and subtractors 25c, 25d. The subtractor 25c subtracts the Q-channel signal from the I-channel signal to cancel the quadrature component (Q-channel component) contained in the I-channel signal. The subtractor 25d subtracts the I-channel signal from the Q-channel signal to cancel the quadrature component (I-channel component) contained in the Q-channel signal.
As will be described later, each of the transversal filters 25a-1-25b-2 is constituted by N-tap FIR filters in which the coefficients can be changed. The coefficients are decided so as to compensate for transmission path distortion. If the I- and Q-channel signals are each expressed by eight bits in 16 QAM, the two high-order bits represent data and the six low-order bits represent the error due to waveform distortion, etc. In case of data that is positive, the relationship between identification threshold values of two high-order bits and digital data is as illustrated in FIG. 21. (1) When a third bit E is "1", the digital data is greater than an intermediate value (the dashed line) of the identification threshold values. (2) When E is "0", the digital data is less than the intermediate value. In order to eliminate the effects of transmission path distortion, it will suffice to perform control in such a manner that the value of the six low-order bits will approach the intermediate value (the ideal value) of the identification threshold values.
Accordingly, in a case where data is positive, control is performed in such a manner that the output data of the transversal filter becomes small if E="1" holds and large if E="0" holds. In a case where data is negative, control is performed in such a manner that the output data of the transversal filter becomes large if E="1" holds and small if E="0" holds. The transversal filters 25a-125b-2 eliminate the influence of transmission path distortion by causing the coefficients of the FIR digital filters to converge toward predetermined values in accordance with the above-described logic.
An example of such a transversal filter is a five-tap transversal filter 250 shown in FIG. 22. The transversal filter 250 includes four delay circuits 251.sub.1 -251.sub.4 for successively delaying input data by one sampling time period (one symbol clock) at a time, coefficient decision/multiplier units 252.sub.0 -252.sub.4 for automatically deciding coefficients C.sub.2 -C.sub.-2 based upon the polarity of the input data and of data D output by each of the delay circuits and an error signal E ("1", "0" of a third bit), and for multiplying the input data and the output data of the delay circuits by the coefficients C.sub.2 -C.sub.-2, and adders 253.sub.1 -253.sub.4 for summing the products from the coefficient decision/multiplier units 252.sub.0 -252.sub.4.
FIG. 23 is a diagram illustrating the details of part of the transversal filter 250. Here the decision/multiplier units 252.sub.0, 252.sub.1 are shown in detail. The decision/multiplier units 252.sub.0, 252.sub.1 include exclusive-OR (EOR) circuits EOR.sub.1, EOR.sub.2, respectively, for obtaining the exclusive-OR between (a) the polarity of the input data and the polarity (the most significant bit MSB) D of the data output by the respective delay circuits and (b) the error signal E of the transversal filter, up/down counters UDC.sub.0, UDC.sub.1, respectively, for incrementing or decrementing the coefficients C.sub.2, C.sub.1 in dependence upon the output of the EOR circuit, and multipliers MLP.sub.0, MLP.sub.1, respectively, for multiplying the input data and delay circuit output data by the coefficients C.sub.2, C.sub.1, respectively.
The coefficient C.sub.2 becomes one larger if the exclusive-OR of the polarity D of the input data and the error signal E is "1" and one smaller if the exclusive-OR is "0". The coefficient C.sub.1 becomes one larger if the exclusive-OR of the output data polarity D of the delay circuit 251.sub.1 and the error signal E is "1" and one smaller if the exclusive-OR is "0". By virtue of this operation, the coefficient values are controlled in such a manner that the value (error) E of the third bit onward of the digital data output by the transversal filter will coincide with the intermediate value (the dashed line in FIG. 21) of the identification threshold levels.
(d) Clock Phase Signal Generator
The clock phase signal generator 26 includes a slope discriminator 30 for discriminating the slope G of the I-channel signal Ich (G="0" holds when the slope is positive and G="1" when the slope is negative), a subtractor 31 for calculating the error E between the input and output signals or the transversal equalizer 25, a delay circuit 32 for delaying the I-channel signal Ich by a predetermined symbol time .tau., a delay circuit 33 for delaying the slope signal, which is output by the slope discriminator 30, by the time .tau., an EOR circuit 34 for taking the exclusive-OR between the signs of the slope G and error signal E, and a loop filter 35, which is constituted by a resistor and capacitor, for smoothing the EOR output signal and outputting an analog clock phase signal CPS. The slope discriminator 30 comprises flip-flop (FF) circuits 30a, 30b and a ROM 30c. The flip-flop circuits 30a, 30b (which act as delay units) successively delay the output signal (I-channel signal) of the AD converter 23 by one symbol time period each, and the ROM (which acts as a comparator) 30c compares the outputs of the flip-flop circuits 30a, 30b to detect the slope of the I-channel signal Ich.
FIG. 24 is a diagram useful in describing clock phase control in a case where the slope G of the I-channel signal is positive (i.e., when G="0" holds). The I-channel signal prior to equalization is shown at 1a, and the I-channel signals after equalization are shown at 1b, 1c. When the I-channel signal is equalized by E in the transversal equalizer 25, the subtractor 31 outputs the error signal E. The sign of the error signal E is negative ("0") if the value before equalization is greater than the value after equalization and positive ("1" if the value before equalization is less than the value after equalization.
If the error signal E is negative ("0"), then the phase of the I-channel 1b signal after equalization lags that of the I-channel signal 1a before equalization by .DELTA.t, as shown by the waveforms in FIG. 24. This indicates that the eye pattern is open to the maximum degree and that the phase of the AD conversion clock (the regenerated clock) lags the optimum phase by .DELTA.t. If the error signal E is positive ("1"), on the other hand, then the phase of the I-channel signal 1c after equalization leads that of the I-channel signal 1a before equalization by .DELTA.t.
Accordingly, in a case where the slope of the I-channel signal is positive (G="0"), as shown in the table TB in FIG. 24, (1) control is performed in a direction that will delay the phase of the regenerated clock by .DELTA.t if the error signal E is positive (="1") (phase shift direction: delay direction="1"), and (2) control is performed in a direction that will advance the phase of the regenerated clock by .DELTA.t if the error signal E is negative (="0") (phase shift direction: advance direction="0").
FIG. 25 is a diagram useful in describing clock phase control in a case where the slope G of the I-channel signal is negative (i.e., when G="1" holds). The I-channel signal prior to equalization is shown at 1a, and the I-channel signals after equalization are shown at 1b, 1c. If the error signal E is negative ("0"), then the phase of the I-channel 1b signal after equalization leads that of the I-channel signal 1a before equalization by .DELTA.t, as shown by the waveforms in FIG. 25. If the error signal E is positive ("1"), on the other hand, then the phase of the I-channel signal 1c after equalization lags that of the I-channel signal 1a before equalization by .DELTA.t. Accordingly, in a case where the slope of the I-channel signal is negative (G="1"), as shown in the table TB in FIG. 25, (1) control is performed in a direction that will advance the phase of the regenerated clock by .DELTA.t if the error signal E is positive (="1") (phase shift direction: advance direction="0"), and (2) control is performed in a direction that will delay the phase of the regenerated clock by .DELTA.t if the error signal E is negative (="0") (phase shift direction: delay direction="1").
Thus, it will suffice to perform phase control in a direction that will advance the clock phase if the output of the EOR circuit 34 is "0" and in a direction that will delay the clock phase if the output of the EOR circuit 34 is "1". Accordingly, if the output of the EOR circuit 34 is smoothed, the smoothed value will take on a value commensurate with the clock phase and, hence, the loop filter 35 will output the phase signal CPS having a value conforming to the clock phase.
(e) Clock Generator
The clock generator 27 has an oscillator, e.g. a voltage-controlled oscillator (VCO) 36, for outputting a clock signal having a frequency conforming to a control signal, and an amplifier 37 for amplifying the clock phase signal CPS to output a control signal. The oscillator 36 controls the clock phase by a control signal conforming to the phase shift of the clock in such a manner that the phase shift becomes zero. A loop comprising the AD converter 23.fwdarw.clock phase signal generator 26.fwdarw.clock regenerating circuit 27.fwdarw.AD converter 23 constructs a PLL that causes the regenerated clock to coincide with the phase of the symbol clock. If a shift develops between the phase of the regenerated clock output by the oscillator 36 and the phase of the symbol clock, the error E is produced between the input and output signals of the transversal equalizer 25. If the error signal E is produced, then the clock phase signal generator 26 uses the slope G of the I-channel signal Ich and the sign of the error signal E to generate the clock phase signal CPS having a value conforming to the phase shift, and the clock regenerating circuit 27 controls the phase of the regenerated clock by the clock phase signal CPS and performs control so as to eliminate the phase difference.
Though the clock regenerating circuit 27 detects the phase shift of the regenerated clock by the clock phase signal generator 26 provided on the side of the I channel, an arrangement may be adopted in which a similar clock phase signal generator 26 is provided on the side of the Q channel and detects the phase shift of the regenerated clock from the Q-channel signal Q.sub.ch.
By virtue of the foregoing operation, the regenerated clock CLK output by the clock regenerating circuit 27 can be made to coincide at all times with the optimum phase at which the eye pattern opens to the maximum extent, thereby making it possible to improve greatly the accuracy of the AD conversion processing executed by the AD converters 23, 24.
(f) Example Using Decision Feedback Equalizer
FIG. 26 is a diagram showing the construction of a receiver demodulator in a case where the transversal filter 25 is constituted by a decision feedback equalizer according to the prior art. Components identical with those shown in FIG. 19 are designated by like reference characters.
The decision feedback equalizer is used to equalize interference between codes caused by frequency selective phasing produced in the propagation path of a digital radio communication system and includes a front equalizer 25A and a back equalizer 25B. The decision feedback equalizer 25 has a center tap coefficient .alpha..sub.0 which acts in the same manner as an AGC circuit. Since the center tap can be external to the equalizer, it is brought to the exterior as AGC circuits 28, 29 in the illustration.
FIG. 27 is a diagram showing the construction of the decision feedback equalizer 25 according to the prior art. The front equalizer 25A is constituted by a front tap coefficient section obtained when the four transversal filters (FIR filters) 25a-1-25a-2, 25b-1-25b-2 are separated into two sections about the center tap. The back equalizer 25B is constituted by a back tap coefficient section.
The front equalizer 25A has FIR filters 25a-11-25a-21 of tap coefficients .alpha..sub.-n -.alpha..sub.-1, .alpha..sub.0, FIR filters 25b-11-25b-21 of tap coefficients .beta..sub.-n -.beta..sub.-1, .beta..sub.0, and subtractors 25c-1, 25d-1. Each FIR filter has a forward-type construction.
The FIR filters 25a-11-25a-21 of the front equalizer 25A each successively delay 8-bit 16 QAM data (in which the high-order two bits represent data and the low-order six bits represent the error due to waveform distortion) of the entered I channel by delay units Z.sup.-1, multiply the output data of the delay units by the tap coefficients .alpha..sub.-n -.alpha..sub.-1, .alpha..sub.0 (.alpha..sub.0 =1 in case of the FIR filter 25a-11), sum the products and output the result. The FIR filters 25b-11-25b-21 successively shift 8-bit 16 QAM data of the entered Q channel by delay units Z.sup.-1, multiply the output data of the delay units by the tap coefficients .beta..sub.-n -.beta..sub.-1, .beta..sub.0, sum the products and output the result. The subtractor 25c-1 subtracts the Q-channel signal from the I-channel signal to thereby cancel the quadrature component (the Q-channel component) contained in the I-channel signal. The subtractor 25d-1 subtracts the I-channel signal from the Q-channel signal to thereby cancel the quadrature component (the I-channel component) contained in the Q-channel signal.
The back equalizer 25B has FIR filters 25a-12-25a-22 of tap coefficients .alpha..sub.1 -.alpha..sub.n, FIR filters 25b-12-25b-22 of tap coefficients .beta..sub.1 -.beta..sub.n, subtractors 25c-2, 25d-2, delay units 25e, 25f for delaying data by one symbol time period each, and discrimination units 25g, 25h for discriminating the levels of the digital data after equalization and feeding the levels back to the FIR filters 25a-12-25a-22, 25b-12-25b-22. Each of the FIR filters 25a-12-25a-22, 25b-12-25b-22 has a backward-type construction.
The FIR filter 25a-12 of the back equalizer 25B successively shifts the I-channel signal, which has entered as feedback, by delay units Z.sup.-1, multiplies the output data of the delay units by the tap coefficients .alpha..sub.1 -.alpha..sub.n, sums the products and outputs the result. The FIR filter 25a-22 successively shifts the I-channel signal, which has entered as feedback, by delay units z.sup.-1, multiplies the output data of the delay units by the tap coefficients .alpha..sub.1 -.alpha..sub.n, sums the products and outputs the result.
The FIR filter 25b-12 successively shifts the Q-channel signal, which has entered as feedback, by delay units Z.sup.-1, multiplies the output data of the delay units by the tap coefficients .beta..sub.1 -.beta..sub.n, sums the products and outputs the result. The FIR filter 25b-22 successively shifts the Q-channel signal, which has entered as feedback, by delay units Z.sup.-1, multiplies the output data of the delay units by the tap coefficients .beta..sub.1 -.beta..sub.n, sums the products and outputs the result.
The subtractor 25c-2 subtracts the Q-channel signal from the I-channel signal to thereby cancel the quadrature component (the Q-channel component) contained in the I-channel signal, and the delay unit 25e outputs the result of subtraction upon delaying it by one symbol timing period. The discriminating unit 25g discriminates the level of the result of subtraction and feeds the result of discrimination back to the FIR filters 25a-12, 25a-22. The subtractor 25d-2 subtracts the I-channel signal from the Q-channel signal to thereby cancel the quadrature component (the I-channel component) contained in the Q-channel signal, and the delay unit 25f outputs the result of subtraction upon delaying it by one symbol timing period. The discriminating unit 25h discriminates the level of the result of subtraction and feeds the result of discrimination back to the FIR filters 25b-12, 25b-22.
In accordance with the decision feedback equalizer, data from which noise and interference components contained in the equalized digital data have been removed is fed back. As a result, tap coefficients can be made to converge correct values and the performance of the equalizer can be improved.
The prior-art radio receivers shown in FIG. 19 and 26 require that the error signal between the input and output signals of the transversal equalizer 25 be calculated. This makes it necessary to provide the delay circuit 32 and subtractor circuit 31 to delay the input signal by the time .tau., which corresponds to the delay time of the transversal equalizer 25. The input signal is expressed by eight bits in case of 16 QAM, and the delay time of the transversal equalizer is 20 symbol clocks (20 sampling periods). Consequently, eight shift registers each having a length of 20 bits are required as the delay circuit 32. This means that the conventional radio receiver involves a large amount hardware. Simplification of the apparatus, therefore, is required.
Further, with the radio receiver according to the prior art, the regenerated clock can be synchronized to the symbol clock owing to the PLL arrangement but there is a need to regenerate a more accurate clock.
When deep phasing occurs, the tap coefficients of the FIR filters constructing the transversal equalizer take on large values. When this occurs, the error due to the phase shift of the clock CLK becomes imbedded and the accuracy of the regenerated clock phase declines. Accordingly, there is a need to regenerate a clock accurately even when phasing occurs.